The efficiency of the manufacturing of microdevices can be enhanced if faulty components are sorted out at an early fabrication stage. Therefore, wafer-level testing is necessary. The methods to achieve this goal are explored in the project PAR-TEST and contain non-electric excitations, measurement techniques, and methods for system parameter determination. The employed enhanced optical techniques for 3D-geometry and vibration measurements will be demonstrated in real production environment.

All activities of PAR-TEST will be published on the MEMUNITY platform. Newest developments and results will also be presented on conferences, workshops and seminars organized either by MEMUNITY or one of the partners of the community. The schedule of important events will be found in the Event section on the MEMUNITY website.

• Read more about goals and competencies of PAR-TEST.
• Find out about the PAR-TEST consortium.
• Enter the Member Area to view and download publications on PAR-TEST.